Revised 2014 Jan 22 8:35 p.m.
Snyder, chapter 9
Outline:
Computer as instruction execution engine
ADD 4000, 2000, 2080 where 4000 and 2000 are the source addresses and 2080 is the destination addressMain points:
This chapter makes references back to the AND operation (ch. 5) and PandA representation (ch. 7); it may be better to cover it after them.
We are going to have small groups act out an assembly language program. Individuals in the group will take on the roles of control unit, registers (to be explained shortly), ALU, and memory.
Our computer is a hypothetical machine called the STUN! computer. STUN is !NUTS spelled backward. STUN! is a reduced instruction set computer (RISC), like the ARM processor (p. 5) and the MIPS processor (p. 275). It is like these, but simplified a little further for classroom use.
Like most real processors, the STUN! machine has registers, which are a small set of storage locations inside the CPU. The ALU operates only on data in registers, not data in memory. Consequently, data in memory must be loaded into a register before it can be used by the ALU. The ALU also places its results in registers, not in memory. The results in registers can then be stored in memory. The STUN! machine has 32 registers, named R0, R1, …, R31.
Memory is addressed by bytes; that is, each 8-bit location has a distinct address. However, for most purposes, the practical unit of storage is four bytes, called a word (32 bits). Therefore, we typically use only memory addresses that are multiples of four (4, 8, 12, 16, etc.).
We will explain the relevant STUN! instructions by example. (In the classroom, it will be best to explain each instruction as needed, as we begin to execute the program.)
Load immediate
li 21, R17 puts the value 21 into the register R17. It is called “load” because it fills up the registers with the value, and “immediate” because the data to be used is found in the instruction without having to look elsewhere (memory or register) for it.
Load word
lw R1, R2 takes the contents of register R1 as an address, obtains the word of memory at that address, and loads the word into register R2. For example, if R1 contains 168, the instruction would load the memory word from address 168 into R2.
Add
add R1, R2, R3 adds the values (whole numbers) contained in registers R1 and R2, and places their sum into register R3.
Set less than
slt R1, R2, R3 compares the values in R1 and R2. If the value in R1 is less than the value in R2, it places a 1 in R3. Otherwise it places a 0 in R3. For example, if R1 contains 7 and R2 contains 77, this instruction would place a 1 in R3, since 7 < 77. The slt instruction is usually used to set up a branch.
Branch not equal zero
bnez R3, 1000 checks the value in register R3; if this value is not equal to 0, it changes the program counter (PC) to 1000, changing the normal flow of instructions; if the value is 0, it does nothing to the PC.
Store word address
swa R10, 1200 takes the word contained in register R10 and stores it in memory at address 1200.
Halt
The halt instruction stops execution of the program. The operating system can then remove the program from memory and run other programs.
Generally, “load” means to place (or “write”) data into a register, and “store” means to place (or “write”) data into a memory location. Source operands are given first, followed by the destination operand; for example, in the add instruction, add R1, R2, R3 means roughly R1 + R2 → R3.
Suggested roles:
Files (in ~/teach/i101/lab/02-assembly):
On handout 1, print.pdf, for the enactment:
;, on the right. The address is where the data or instruction is located. Comments are for explanation to humans and are ignored by the computer. Any line beginning with ; is all comment.Discussion after the enactment:
Additional files, for post-enactment lecture and discussion (print2.pdf):
addnums.ods — spreadsheet sum function is similar to Python’s but uses cell addressing
Is it important to understand the Java or Python instructions? For this course, no. Python and Java are covered in INFO I210 and I211, respectively.